The invention relates to a circuit and technique to stall the communication of data over a double pumped bus.
As the performance of microprocessors advance, so does the complexity of their designs. As a result of this complexity, more conductive traces, or wires, may be present to route signals across the semiconductor die on which the microprocessor is fabricated. However, it is possible there may be more signals to be routed than there is room in the die to accommodate the corresponding wires.
One solution to this dilemma is to reduce the number of wires that are used to communicate different sets of data. One such arrangement is a double pumped bus, an arrangement in which data is communicated across a single wire in a time multiplexed fashion. Thus, one set of data (that is associated with a particular circuit) is communicated during time slots that are interleaved with other time slots that are used to communicate another set of data (that is associated with another circuit). In this manner, with a double pumped bus, bits from one set of data are communicated to the wire in synchronization with one phase of a clock signal, and bits from another set of data are communicated in synchronization with another phase of the clock signal. For example, one set of data may be communicated across the wire in response to the positive edges (i.e., the rising edges having positive slopes) of a clock signal, and another set of data may be communicated across the wire in response to the negative edges (i.e., the falling edges having negative slopes) of the clock signal.
As a more specific example, FIG. 1 depicts a double pumped bus system 10 to communicate bits of data across a wire 26 between two double pumped bus cells 12 and 14. It is assumed that the cells 12 and 14 share a common ground. As an example, during the logic zero states of a clock signal (called CLK), the cell 12 drives a signal on the wire 26 so that the signal indicates bits of data from a first data set, and during the logic one states of the CLK signal, the cell 12 drives the signal on the wire 26 so that the signal indicates bits of data from a second data set. The cell 14 decodes the bits of data that are indicated by the signal on the wire 26 and may retransmit the bits of data in a time multiplexed fashion by driving a signal on another wire 27 in a manner similar to that described above. It is noted that, as described below, the cell 14 may be replicated for purposes of forming a larger double pumped system that communicates bits of data over several wires in synchronization with the CLK signal.
As an example, the cell 12 may include a bit latch 16 to latch and temporarily store bits of data from a first set of data and another bit latch 18 to temporarily store bits of data from a second set of data. In this manner, the input terminal of the bit latch 16 may receive a signal (called DATA1) that indicates the bits of the first data set, and the input terminal of the bit latch 18 may receive a signal (called DATA2) that indicates the bits of the second data set. The bit latch 18 is connected to latch bits in response to the positive edges of the CLK signal, and the bit latch 16 is connected to latch bits in response to the negative edges of the CLK signal.
Due to this arrangement, the bit latch 16 responds to each negative edge of the CLK signal by latching the DATA1 signal to store a new bit of the first data set. During the logic zero state of the clock of the CLK signal, the bit latch 16 furnishes a signal (at its non-inverted output terminal) that indicates its stored bit. The bit latch 18 responds to each positive edge of the CLK signal by latching the DATA2 signal to store a new bit of the second data set. During the logic one state of the CLK signal, the bit latch 18 furnishes a signal (at its non-inverted output terminal) that indicates its stored bit.
A multiplexer 20 of the cell 12 selects the output terminals of the bit latches 16 and 18 in response to the above-described logical states of the CLK signal to furnish the bits to the wire 26. As a result, the signal that is furnished by the multiplexer 20 indicates the bits from the first and second data sets in a time multiplexed fashion. It is noted that the cell 14 may have a similar design to the cell 12 except that the input terminals of the bit latches 16 and 18 of the cell 14 are connected together to receive the same signal from the wire 26. Because the bit latch 18 of the cell 14 latches in response to the positive edges of the CLK signal and the bit latch 16 of the cell 14 latches in response to the negative edges of the CLK signal, the bit latches 16 and 18 latch the signal from the wire 26 in alternating time slices to de-multiplex the data. The cell 14 places the bits back into the time multiplexed order for purposes of transmitting the bits across the other wire 27.
Referring to FIG. 2, several cells 12 and 14 (cells 14a, 14b and 14c, as examples) may be serially coupled together to from a chain to relay data between the cells 14 using the double pumped technique that is described above. In this manner, the cell 12 is the first in the chain, and the cells 14 precede the cell 12 in the chain. As an example, FIG. 3 depicts signals called DP1, DP2 and DP3 that are furnished by the cells 12, 14a and 14b, respectively, and illustrate the propagation of data bits between the cells 12 and 14. For example, referring to FIG. 3, the CLK signal has a negative edge at time T1, and in response to this negative edge, the cell 12 latches a bit (represented by the portion 50 of the DATA1 signal) for the first data set. At time T2, the CLK signal has a positive edge, an edge that causes the cell 12 to latch a bit (represented by the portion 52 of the DATA2 signal) for the second data set. After time T1 during the logic zero state of the CLK signal, the cell 12 begins furnishing the bit 50 to the cell 14a. It is noted that the bit 50 may not appear until after a slight propagation delay, as depicted in FIG. 3. After time T2 during the logic one state of the CLK signal, the cell 12 begins furnishing the bit 52 to the cell 14a, as depicted in FIG. 3. The cells 14a and 14b then relay the bits 50 and 52 in a time multiplexed fashion.
Unfortunately, the above-described cells only accommodate free flowing data. In this manner, the conventional double pumped bus cell does not have the capability to selectively block the flow of bits from a particular data set.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.